The present invention relates to a communication DMA device, and more specifically to a communication DMA device that frees the data bus from the CPU and allows image data stored in a DRAM to be output via a communication channel in outputting image data of an image taken by a digital still camera to a personal computer.
Normally, in a digital still camera, image data of an image taken can be stored in a DRAM, and the CPU can read the stored image data and transfer the data to a recording medium to be saved as an image, or the data can be transferred to a display device to project the image. A DRAM can utilize the area other than the image data area as a work area for various processing. For instance, when image data is transferred to a personal computer by serial communication interface, a recording medium stores image data usually compressed in JPEG format, image data of a suitable size for transmission is read therefrom and is temporarily written into the work area of the DRAM, and thereafter the CPU reads the image data as transmission data and writes the data into a communication circuit, thereby the transmission data is serially output.
When the transmission of all image data to the work area is completed by repeating the above processing, image data of a suitable size for next transmission is read out and is written into the DRAM, and the same processing as above is repeated to continue the transmission.
In order to speed up the communication, however, the CPU must be monopolized by the communication control so that other processing cannot be performed during this time. In addition, the CPU seldom controls a camera using a 8 bit bus, but generally controls it using a 16 bit to 32 bit bus.
On the other hand, communication processing generally involves a unit of 8 bits, and the well-known asynchronous/synchronous communication chip 8251 is also processed by 8 bits. Therefore, supposing that the CPU that controls utilizes a 32 bit bus, the data is divided into 4 bytes, i. e. bits 7 to 0, 15 to 8, 23 to 16, and 31 to 24. Although the data of bits 7 to 0 can be directly written into the communication circuit, data from bits 31 to 8 must be written into the communication circuit after being allocated again to bits 7 to 0. Thus, a greater load is imposed upon the CPU than when 32 bits of data is transferred at once, and as a result, the processing speed of the CPU becomes slower. In particular, when transferring image data directly from the camera to a printer, a very high-speed transmission is required, which has surpassed the processing capability of the CPU.
Thus, the present invention provides a communication DMA device that lightens the load for the CPU while allowing a high-speed transfer.
The present invention is a communication DMA device, with a CPU, a communication circuit and a memory sharing a data bus, for outputting to the outside via the communication circuit transmission data stored in the memory; wherein the information indicating an area of the memory in which data to be transmitted is stored, the information indicating the capacity of the data to be transmitted, and the information indicating the start of communication are stored in a register; release of the data bus from the CPU is requested in order to allow reading of the transmission data of a prescribed bit width from the memory; the data bus is immediately connected to the CPU by a bus switching request circuit after the termination of the read operation; the data read from the memory via the data bus based on the information stored in the register is temporarily stored in a temporary storage circuit; and the data of a prescribed bit width stored temporarily is divided and output to the outside via the communication circuit several bits at a time.
Thus, according to the present invention, in performing the serial communication control, the CPU can carry out the transmission by executing several instructions, and the CPU is kept from being monopolized by the communication control so that the time spent on it can be used for other processing. Moreover, communication data once DMAed, or direct-memory-accessed is processed for transmission by monitoring the flag of the communication circuit regardless of the state of the data bus so that transmission with no intermission between one transmission data and another is achieved. Furthermore, since the period during which DMA for communication monopolizes the data bus can made short, such monopolization seldom interferes with the CPU processing, and as a result, not only the high speed communication but also the high speed processing of the overall system is achieved.
In a more preferred embodiment, the number of times data is read from the memory or the number of times data is provided to the communication circuit is counted by a counting circuit, and the count value is output to the data bus to allow the CPU to read the count value via the data bus.
In another preferred embodiment, when some other device requests for release of the data bus and when the bus release request is made first by the other device, the data bus is freed for the other device and the communication DMA device carries out processing after processing by the other device is complete; and when the bus release request is made first by the communication DMA device and the other device requests for bus release during processing by the communication DMA device, the processing is immediately stopped by the communication DMA device, the data bus is handed over to the other device, and after processing by the other device is complete, the data bus is returned to the communication DMA device and the processing resumes.